Chip Architecture
SoC, CPU and GPU architecture exploration: blocks, interconnect and performance, power and area estimation.
Details →Product families
Eight families on one Sigma platform, in build order. Chip architecture ships first because it helps CPU, GPU and SoC teams before foundry signoff is required; later families light up as their correlation benchmarks pass.
Digital Design & Verification
RTL entry, compiled simulation, waveform debug and lint for SystemVerilog, Verilog and VHDL.
Details →Synthesis & Static Timing
Logic synthesis to gates, SDC constraints, Liberty models and static timing analysis.
Details →Physical Design & Verification
Floorplan, placement, clock tree, routing, extraction, DRC and LVS over GDSII, OASIS, LEF and DEF.
Details →Analog & Device
SPICE-class circuit simulation, device modeling and process-device physics.
Details →Package & Board Multiphysics
Thermal, power integrity, signal integrity and EM for chiplets, packages and boards.
Details →General Multiphysics
Structural FEA, CFD and electromagnetics on the shared GPU solver platform.
Details →Mechanical CAD
Parametric modeling and STEP-class interchange for enclosures and mechanics.
Details →